Ascent Pattern Set			15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	
																			
CCD:	F4320		HP(15)	HP(14)	HP(13)	HP(12)	HP(11)	HP(10)	HP(9)	HP(8)	HP(7)	HP(6)	HP(5)	HP(4)	HP(3)	HP(2)	HP(1)		
System:	Ascent 		- step 0 must be final resting  state																
Pattern	FKHR4A 1.5 MHZ																		
Date:	4/6/2012	Time (nS)	Latching	ADD/FIFO	RIGHT	FIFO	Channel	SAM 2L	SAM 1L	SAM 2R	SAM 1R	ADCLK	SW	S3	S2	S1	R	Stop	Row
	Mask		0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	0	
	BIN 1	0	0	0	0	0	0	0	0	0	0	0	1	0	0	1	1	0	1
		10	0	0	0	0	0	0	0	0	0	0	1	0	0	1	1	0	2
		20	0	0	0	0	0	0	0	0	0	0	1	0	0	1	1	0	3
		30	0	0	0	0	0	0	0	0	0	0	1	0	0	1	1	0	4
		40	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	0	5
		50	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	0	6
		60	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	0	7
		70	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	0	8
		80	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	0	9
		90	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	0	10
		100	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	0	11
		110	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	0	12
		120	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	0	5
		130	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	0	6
		140	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	0	7
		150	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	0	8
		160	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	0	9
		170	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	0	10
		180	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	0	11
		190	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	0	12
		200	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	0	5
		210	0	0	0	0	0	0	0	0	0	1	1	0	0	1	0	0	6
		220	0	0	0	0	0	0	0	0	0	1	1	0	0	1	0	0	7
		230	1	0	0	0	0	0	0	0	0	1	1	0	0	1	0	0	8
		240	0	0	0	0	0	0	0	0	0	1	1	0	0	1	0	0	9
		250	0	0	0	0	0	0	1	0	1	1	1	0	0	1	0	0	10
		260	0	0	0	0	0	0	1	0	1	1	1	0	0	1	0	0	11
		270	0	0	0	0	0	0	1	0	1	1	1	0	0	1	0	0	12
		280	0	0	0	0	0	0	1	0	1	1	1	0	0	1	0	0	13
		290	0	0	0	0	0	0	1	0	1	1	1	0	0	1	0	0	14
		300	0	0	0	0	0	0	1	0	1	1	1	0	0	1	0	0	15
		310	0	0	0	0	0	0	1	0	1	1	1	0	0	1	0	0	16
		320	0	0	0	0	0	0	0	0	0	1	1	0	0	1	0	0	17
		330	0	0	0	0	0	0	0	0	0	1	1	0	0	1	0	0	18
		340	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	19
		350	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	20
		360	1	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	21
		370	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	13
		380	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	14
		390	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	15
		400	0	0	0	0	0	1	0	1	0	0	0	0	1	0	0	0	16
		410	0	0	0	0	0	1	0	1	0	0	0	0	1	0	0	0	17
		420	0	0	0	0	1	1	0	1	0	1	0	0	1	0	0	0	18
		430	0	0	0	0	1	1	0	1	0	1	0	0	1	0	0	0	19
		440	1	0	0	0	1	1	0	1	0	1	0	0	1	0	0	0	20
		450	0	0	0	0	1	1	0	1	0	1	0	0	1	0	0	0	21
		460	0	0	0	0	1	1	0	1	0	1	0	0	1	0	0	0	22
		470	0	0	0	0	1	1	0	1	0	1	0	0	1	0	0	0	23
		480	0	0	0	0	1	1	0	1	0	1	0	0	1	0	0	0	24
		490	0	0	0	0	1	1	0	1	0	1	0	0	1	0	0	0	25
		500	0	0	0	0	1	1	0	1	0	1	0	0	1	0	0	0	26
		510	0	0	0	0	1	1	0	1	0	1	0	0	1	0	0	0	27
		420	0	0	0	0	1	0	0	0	0	1	0	0	1	0	0	0	18
		430	0	1	0	0	1	0	0	0	0	1	0	0	1	0	0	0	19
		440	0	0	0	0	1	0	0	0	0	1	0	0	1	0	0	0	20
		450	0	0	0	0	1	0	0	0	0	0	0	0	1	0	0	0	21
		460	0	0	0	0	1	0	0	0	0	0	0	0	1	0	0	0	22
		470	1	0	0	0	1	0	0	0	0	0	0	0	1	0	0	0	23
		480	0	0	0	0	1	0	0	0	0	0	0	0	1	0	0	0	24
		490	0	0	0	0	1	0	0	0	0	0	0	0	1	0	0	0	25
		500	0	0	0	0	1	0	0	0	0	0	0	0	1	0	0	0	26
		510	0	0	0	0	1	0	0	0	0	0	0	0	1	0	0	0	27
		520	0	0	0	0	1	0	0	0	0	0	0	0	1	0	0	0	28
		530	0	0	0	0	1	0	0	0	0	0	0	0	1	0	0	0	29
		540	0	0	0	0	1	0	0	0	0	0	0	0	1	0	0	0	30
		550	0	0	0	0	1	0	0	0	0	0	0	0	1	0	0	0	31
		560	0	0	0	0	1	0	0	0	0	0	0	0	1	0	0	1	32
	END	570	0	0	0	0	1	0	0	0	0	0	0	0	1	0	0	0	33
